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| p10c68/p11c68 1 ds3600-1.2 september 1992 preliminary information p10c68/p1 1c68 ) cmos/snos nvsram high performance 8 k x 8 non-vola tile st a tic ram ! the p10c68 and p11c68 are fast static rams (35 and 45 ns) with a non-volatile electically-erasable prom (eeprom)cell incorporating in each static memory cell. the sram can be read and written an unlimited number of times while independent non-volatile data resides in prom. on the p10c68 data may easily be transferred from the sram to the eeprom (store) and from the eeprom backto the sram ( recall) using the ne (bar) pin. the store and recall cycles are initiated through software sequences on the p11c68. these devices combine the high performance and ease of use of a fast sram with the data integrity of non- volatility. the p10c68 and p11c68 feature the industry standard pinout for non-volatile rams in a 28-pin 0.3-inch plastic andceramic dual-in-line packages. features non-volatile data integrity 10 year data retention in eeprom 35ns and 45ns address and chip enable access times 20ns and 25ns output enable access unlimited read and write to sram unlimited recall cycles from eeprom 10 4 store cycles to eeprom automatic recall on power up automatic store timing hardware store protection single 5v 10% operation available in standard package 28-pin 0.3-inch dil plastic and ceramic commercial and industrial temperature ranges pin name function a 0 - a 12 address inputs write enable dq 0 - dq 7 data in/out chip enable output enable v cc power (+5v) v ss ground pin 1 non volatile enable p10c68 pin 1 n/c no connection p11c68 12 3 4 5 6 7 8 9 10 11 1213 14 2827 26 25 24 23 22 21 20 19 18 17 16 15 vw nc a a a g a e dq dq dq dq dq 76 5 4 3 89 11 10 cc ne aa a a a a a a a dqdq dq v 127 6 5 4 3 2 1 0 0 1 2 ss "# $$% % & ordering information(see back page) p10c68/p11c682 f # '#$ ( $) #* r o w d e c o d e r i n p u t b u ff e r s st a tic ram arra y 256 x 256 eeprom arra y 256 x 256 column i/o column decoder st ore/ recall control g ne (p10c68 only) e w a 0 a 1 a 2 a 10 a 11 st ore recall a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 12 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 p10c68/p11c68 3 value parametersupply voltage input logic '1' voltage input logic '0' voltage ambient operating temperature commercialindustrial symbol v cc v ih v il t amb t amb min. 2.2 v ss -0.5 0 -40 conditions all inputsall inputs max. v cc +0.5 0.8 +70+85 typ. 5.0 dc operating conditionsdc electrical characteristics commercial temperature range test conditions (unless otherwise stated): tamb = 0 c to 70 c, vcc = +5v (see notes 1, 2 and 3) characteristicaverage power supply current average power supply current during store cycle average power supply current (standby, cycling ttl input levels) average power supply current (standby, stable cmos input levels) input leakage current (any input) off state output leakage current output logic '1' voltage output voltage '0' voltage symbol i cc1 i cc2 i sb1 i sb2 i ilk i olk v oh v ol value units mama ma ma ma ma a a vv conditions t avav = 35ns t avav = 45ns all inputs at v in 0.2v t avav = 35ns t avav = 45ns e(bar) v ih , all other inputs cyclinge (bar) (v cc -0.2v), all other inputs at v in 0.2v or (v cc - 0.2v)v cc = max, v in = v ss to v cc v cc = max, v in = v ss to v cc i out = 4ma i out = 8ma max. 7565 50 23 20 1 1 5 0.4 min. 2.4 notes1. i cc1 is dependent on output loading and cycle rate. the specified values are obtained with outputs unloaded. 2. bringing e (bar) v ih will not produce standby currents levels until any non-volatile cycle in progress has timed out. see mode selection table. 3. i cc2 is the average current required for the duration of the store cycle (t store ) after the sequence that initiates the cycle. absolute maximum ratings voltage on typical inputrelative to vss -0.6v to 7.0v voltage on dq0-7 and g(bar) -0.5v to (vcc + 0.5v) temperature under bias -55 c to + 125 c storage temperature -65 c to + 150 c power dissipation 1w dc output current 15ma (one output at a time, one second duration) note stresses greater than those listed in the absolute maximum ratings may cause permanent damage to thedevice. these are stress ratings only; functional operation of the device at any other conditions than those indicated in the operational sections of the specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect reliability. units vv v c c p10c68/p11c684 characteristicaverage power supply current average power supply current during store cycle average power supply current (standby, cycling ttl input levels) average power supply current (standby, stable cmos input levels) input leakage current (any input) off state output leakage current output logic '1' voltage output voltage '0' voltage industrial temperature range test conditions (unless otherwise stated): tamb = -40?c to 70?c, vcc = +5v 10% (see notes 4, 5 and 6) symbol i cc1 i cc2 i sb1 i sb2 i ilk i olk v oh v ol value units mama ma ma ma ma a a vv conditions t avav = 35ns t avav = 45ns all inputs at v in 0.2v t avav = 35ns t avav = 45ns e(bar) v ih , all other inputs cyclinge (bar) (v cc -0.2v), all other inputs at v in 0.2v or (v cc - 0.2v)v cc = max, v in = v ss to v cc v cc = max, v in = v ss to v cc i out = 4ma i out = 8ma max. 8075 50 27 23 1 1 5 0.4 min. 2.4 input pulse levelsinput rise and fall times input and output timing reference levels output load v ss to 3v 5ns 1.5vsee figure 3 ac test conditionscapacitance t amb = 25 c, f = 1.0mhz (see note 7) parameterinput capacitance output capacitance symbol c in c out units pfpf max. 57 conditions v=0 to 3v v=0 to 3v note7. these parameters are characterised but not 100% tested. notes4. i cc1 is dependent on output loading and cycle rate. the specified values are obtained with outputs unloaded. 5. bringing e (bar) v ih will not produce standby currents levels until any non-volatile cycle in progress has timed out. see mode selection table. 6. i cc2 is the average current required for the duration of the store cycle (t store ) after the sequence that initiates the cycle. 5.0v 480 ohms 30pincluding scope and fixture 255 ohms output "# + %% # p10c68/p11c68 5 sram memory operation test conditions (unless otherwise stated):commercial and industrial temperature range tamb = -40 c to + 85 c, vcc = + 5v 10% read cycles 1 and 2 (see note 8) notes8. e (bar), g (bar) and w (bar) must make the transition between vih(min) to vil(max), or vil(max) to vih(min) in a monotonic fashion. ne (bar) must be vih during entire cycle. 9. for read cycle 1 and 2, w (bar) and ne (bar) must be high for entire cycle. 10. device is continuously selected with e (bar) low, and g (bar) low. 11. measured 200mv from steady state output voltage. load capacitance is 5pf. 12. parameter guaranteed but not tested. t avav t a vqv t axqx t whqv address dq (da t a out) w da t a v alid "# ,-+ .'- %*# #* % ! standard t elqv t avav t avqv t glqv t axqx t elqx t ehqz t glqx t ghqz t elicch t ehiccl t whqv alternative t acst rc t aa t oe t oh t lz t ohz t olzt hz t pa t ps t wr parameter chip enable access timeread cycle time address access time output enable to data valid output hold after address change chip enable to output active chip disable to output inactive output enable to output active outout disable to output inactive chip enable to power active chip disable to power standby write recovery time units nsns ns ns ns ns ns ns ns ns ns ns notes 9 1011 11 12 12 p10c68-45p11c68-45 p10c68-35P11C68-35 symbol min. 45 55 0 0 max. 4545 25 25 20 25 55 min. 35 55 0 0 max. 3535 20 20 15 25 45 p10c68/p11c686 write cycle 1 : w (bar) controlled (see notes 8 and 13) commercial and industrial temperature range t whqv w t avav t elqv t elqx t ehiccl t ehqz t ghqz t glqx t elicch da t a v alid st andby active dq (da t a out) address e g i cc t glqv f # ,-+ .'- %*# #* % ! standard t avav t wlwh t elwh t dvwh t whdx t avwh t avwl t whax t wlqz t whqz alternative t wc t wp t cw t dw t dh t aw t as t wr t wz t ow parameter write cycle timewrite pulse width chip enable to end of write data set-up to end of write data hold after end of write address set-up to end of write address set-up to start of write address hold after end of write write enable to output disable output active after end of write units nsns ns ns ns ns ns ns ns ns notes11, 14 p10c68-45p11c68-45 p10c68-35P11C68-35 symbol min. 4535 35 30 0 35 00 5 max. 35 min. 4535 35 30 0 35 00 5 max. 35 notes13. e (bar) or w (bar) must be vih during address transitions. 14. if w (bar) is low when e (bar) goes low, the outputs remain in the high impedance state. p10c68/p11c68 7 t avav t el wh t a vwh t wl wh t a vwl t dvwh t whdx t whqx t wlqz t whax address e w da t a in da t a out da t a v alid high impedance previous da t a f # /,01- .'- 2 / (! $% %*# #* % ! standard t avav t wleh t eleh t dveh t ehdx t aveh t ehax t avwl alternative t wc t wp t cw t dw t dh t aw t wr t as parameter write cycle timewrite pulse width chip enable to end of write data set-up to end of write data hold after end of write address set-up to end of write address hold after end of write address set-up to start of write units nsns ns ns ns ns ns ns notes p10c68-45p11c68-45 p10c68-35P11C68-35 symbol min. 4535 35 30 0 35 00 max. min. 4535 35 30 0 35 00 max. write cycle 2 : e (bar) controlled (see notes 8 and 13) t avav t eleh t a vel t ehax t a veh t wleh t dveh t ehdx address e w da t a in da t a out da t a v alid high impedance f # 3 /,01- .'- 2 - (! $% %*# #* % ! p10c68/p11c688 5.0v3.3v aut o recall st ore inhibit v cc t "# +%*%$ ,-+'' 14,- 5(% non-volatile memory operation of p10c68 mode selection x h l h ll h h ll l l l l x l x l h l h x hh ll l x power standbyactive active active i cc2 active mode not selectedread ram write ram non-volatile recall (note 15) non-volatile store no operation note15. an automatic recall also takes place on chip power-up, starting when vcc exceeds 3.3v, and taking t recall from the time at which vcc exceeds 3.3v. vcc must not drop below 3.3v once it has exceeded it for the recall to functionproperly. standard t wlqx t ghnl t nlwl t wlnh t elwl alternative t store t wc parameter store cycle timeoutput disable set-up to ne (bar) fall non-volatile set-up to write low write low to ne (bar) rise chip enable set-up symbol notes 1718 units ms nsns ns ns min. 00 45 0 max. 10 min. 00 45 0 max. 10 store cycle 1 : w (bar) controlled (see note 16) p10c68-35 p10c68-45 p10c68/p11c68 9 store cycle 2 : e (bar) controlled (see note 13) standard t elqx1 t nlel t wlel t elnh t ghel alternative t store t wc parameter store cycle timene (bar) set-up to chip enable write enable wet-up to chip enable chip enable to ne (bar) rise output disable set-up to e (bar) fall symbol notes 1718 units ms nsns ns ns min. 00 45 0 max. 10 min. 00 45 0 p10c68-35 p10c68-45 max. 10 notes16. e (bar), g (bar), ne (bar) and w (bar) must make the transition between vih(max) to vil(max), or vil(max) to vih(min) in a monotonic fashion. 17. measured with w (bar) and ne (bar) both returned high, and g (bar) returned low. note that store cycles are inhibited/abort ed by vcc <3.3v (store inhibit).18. once twc has been satisfied by ne (bar), g (bar), w (bar) and e (bar) the store cycle is completed automatically, ignoring all inputs. any of ne (bar), g (bar), w (bar) or e (bar) may be used to terminate the store initiation cycle. t ghnl t nl wl t wlnh t el wl t wlqx ne g w e dq (da t a out) high impedance "# 14,- .'- 2 / (! $% %*# #* % ! t ghel t nlel t elnh t wlel t elqx1 ne w e dq (da t a out) high impedance g "# 14,- .'- 2 - (! $% %*# #* % ! p10c68/p11c6810 standard t nlqx t nlnh t glnl t whnl t elnl t nlqz alternative t recall t rc parameter recall cycle timerecall initiation cycle time output enable set-up write enable set-up chip enable set-up ne (bar) fall to output inactive units s s nsns ns ns notes 1920 symbol min. 25 00 0 max. 2025 min. 25 00 0 max. 2025 p10c68-45 p10c68-35 p10c68 recall cycle 1 : ne (bar) controlled (see note 16) p10c68 recall cycle 3 : g (bar) controlled (see note 16) alternative t recall t rc parameter recall cycle timerecall initiation cycle time ne (bar) set-up write enable set-up chip enable set-up units s nsns ns ns notes 1920 symbol min. 25 00 0 max. 20 min. 25 00 0 max. 20 p10c68-45 p10c68-35 standard t glqx2 t glnh t nlgl t whgl t elgl notes19. measured with w (bar) and ne (bar) both returned high, and g (bar) returned low. address transitions may not occur on any address pin during this time. 20. once t rc has been satisfied by ne (bar), g (bar), w (bar) and e (bar) the recall cycle is completed automatically. any of ne (bar), g (bar) or e (bar) may be used to terminate the recall initiation cycle. p10c68 recall cycle 2 : e (bar) controlled (see note 16) alternative t recall t rc parameter recall cycle timerecall initiation cycle time ne (bar) set-up output enable set-up write enable set-up units s nsns ns ns notes 1920 symbol min. 25 00 0 max. 20 min. 25 00 0 max. 20 p10c68-45 p10c68-35 standard t elqx2 t elnh t nlel t glel t whel p10c68/p11c68 11 t glnl t nlhn t whnl t nlqx ne e dq (da t a out) high impedance w t elnl t nlqz g f # ,-+'' .'- 2 - (! $% %*# #* % ! t glel t nlel t whel t elqx2 e dq (da t a out) high impedance w g ne t elnh "# ,-+'' .'- 2 - (! $% %*# #* % ! t whgl t nlgl t elgl t glqx2 dq (da t a out) high impedance w g ne t glnh e "# ,-+'' .'- 2 - (! $% %*# #* % ! p10c68/p11c6812 notes 22 21, 2221, 22 21, 22 21, 22 21, 22 20 21, 2221, 22 21, 22 21, 22 21, 22 21 power standby activeactive active i cc2 active i/o output high z output data input data output dataoutput data output data output data output data output high z output dataoutput data output data output data output data output high z mode not selectedread ram write ram read ram read ram read ram read ram read ram non-volatile store read ram read ram read ram read ram read ram non-volatile recall a 12 -a 0 (hex) xx x 00001555 0aaa 1fff 10f0 0f0f 00001555 0aaa 1fff 10f0 0f0e h ll l l x h l hh standard t avav t axav t avqz t avel t eleh t ehax alternative t acs t skew t elqz t store t recall t ae t ep t ea parameter read cycle timeskew between sequentially adjacent addresses address valid to output inactive store cycle time recall cycle time address set-up to chip enable chip enable pulse width chip disable to address change units nsns ns ms s nsns ns notes 2325 26 26, 30 2727 27 symbol min. 45 0 45 0 max. 5 7510 20 min. 35 0 35 0 max. 5 7510 20 p11c68-45 P11C68-35 notes23. skew spec may be avoided by using e (bar) (store/recall cycle 2). 24. w (bar) v ih during entire address sequence to initiate a non-volatile cycle. required address sequences are shown in the mode selection table. 25. once the software store or recall cycle is initiated, it completes automatically, ignoring all inputs. 26. measured with w (bar) high, g (bar) low and e (bar) low. note that store cycles (but not recalls) are aborted by vcc < 3.3v (store inhibit). 27. e (bar) must make the transition between v ih (max) to v il (max), or v il (max) to v ih (min) in a monotonic fashion. 28. chip is continuously selected with e (bar) low. 29. addresses 1 through 6 are found in the mode selection table. address 6 determines whether the p11c68 performs a store or recall. a recall cycle is performed automatically at power up when v cc exceeds 3.3v. v cc must not drop below 3.3v once it has exceeded it for the recall to function properly, t recall is measured from the point at which v cc exceeds 3.3v. 30. address transitions may not occur on any address pin during this time. notes21. the six consecutive addresses must be in order listed - (0000, 1555, 0aaa, 1fff, 10f0, 0f0f) for a store cycle or (0000, 1555, 0aaa, 1fff, 10f0, 0f0e) for a recall cycle. w (bar) must be high during all six consecutive cycles. seestore cycle and recall cycle tables and diagrams for further details. 22. i/o state assumes that g (bar) v il . activation of non-volatile cycles does not depend on the state of g (bar). store / recall cycles 1 and 2 (see notes 24 and 29) non-volatile memory operation of p11c68 mode selection p10c68/p11c68 13 operating notes note: references to ne (bar) should be taken as applying to p10c68 only and can be ignored for p11c68. the devices have two separate modes of operation: sram mode and non-volatile mode. in sram mode, the memoryoperates as an ordinary static ram. while in non-volatile mode, data is transferred in parallel from sram to eeprom or from eeprom to sram. sram read the devices perform a read cycle when ever e (bar) and g (bar) are low and ne (bar) and w (bar) are high. theaddress specified by the thirteen address pins a 0-12 determine which of the 8192 data bytes will be accessed. when theread is initiated by an address transistion, the outputs will be valid after a delay of t avqv (read cycle 1). if the read is initiated by e (bar) or g (bar), the outputs will be valid at t elqv or t glqv , whichever is later. (read cycle 2). the data outputs will repeatedly respond to address changeswithin the t avqv access time without the need for transitions on any control input pins and will remain valid until anotheraddress change or until e (bar) or g (bar) is brought high or w (bar) or ne (bar) is brought low. sram write a write cycle is performed whenever e (bar) and w (bar) are low and ne (bar) is high. the address inputs must bestable prior to entering the write cycle and must remain stable until either e (bar) or w (bar) go high at the end of the cycle. the data on the eight pins dq 0-7 , will be written into the memory location specified by the address inputs if valid t dvwh before the end of a w (bar) controlled write or t dveh before the end of an e (bar) controlled write. "# 14,-6,-+'' $ $ - (! $% %*# #* % 3! t skew t avav t avav t avav t st ore / t recall t a vqz inv alid address 1 address 2 address 6 da t a v alid d a t a v a lid da t a v a lid da t a v alid high impedance address dq (da t a out) "# 14,-6,-+'' $ $ + $% %*# #* % 3! address 1 address 6 t avav t avav address e t eleh t a vel t ehax t st ore / t recall da t a v alid da t a v alid da t a v alid high impedance dq (da t a out) t elqz p10c68/p11c6814 it is recommended that g (bar) be kept high during the entire write cycle to avoid data bus contention on thecommon i/o lines. if g (bar) is left low, internal circuitry will turn off the output buffers t whqz after w (bar) goes low. non-volatile store - p10c68 a store cycle is performed when ne, (bar) e (bar) and w (bar) are low and g (bar) is high. while any sequence toachieve this state will initiate a store, only w(bar) initiation (store cycle 1) and e (bar) initiation (store cycle 2) are practical without risking an unintentional sram write that would disturb sram data. during the store cycle, previous non-volatile data is erased and the sram contents are then programmed into non-volatile elements. once a store cycle is initiated, further input and output is disabled and the dq 0-7 pins are tri-stated until the cycle is completed. if e (bar) and g (bar) are low and w (bar) and ne (bar) are high at the end of the cycle, a read will be performedand the outputs will go active, signalling the end of the store. the p10c68 will not be activated into either a store or recall cycle by the software sequence required for thep11c68. hardware protect - p10c68 the p10c68 offers two levels of protection to suppress inadvertent store cycles. if the clock signals remain in thestore condition at the end of a store cycle, a second store cycle will not be started. the store will be initiated only after a high to low transition on ne (bar)because the store cycle is initiated by an ne (bar) transition, powering- up the chip with ne (bar) low will not initiate a store cycle either. in addition to multi-trigger protection, the p10c68 offers hardware protection through vcc sense. a store cycle will not be initiated, and one in progress will discontinue, if vcc goes below 3.3v. non-volatile recall - p10c68 a recall cycle is performed when e (bar), g (bar) and ne (bar) are low and w (bar) is high. like the store cycle,recall is initiated when the last of the four clock signals goes to the recall state. once initiated, the recall cycle will take t nlqx to complete, during which all inputs are ignored. when the recall completes, any read or write state onthe input pins will take effect. internally, recall is a two step procedure. first the sram data is cleared and second, the non-volatile informationis transferred into the sram cells. the recall operation in no way alters the data in the non-volatile cells. the non-volatile data can be recalled an unlimited number of times. address transitions may not occur during the recall cycle. like the store cycle, a transition must occur on the ne (bar) pin to cause a recall, preventing inadvertent multi-triggering. on power-up, once vcc exceeds vcc sense voltage of 3.3v, a recall cycle is automatically initiated. the voltage on the vcc pin must not drop below 3.3v once it has risen above it in order for the recall to operate properly. due to the automatic recall, sram operation cannot commence until t nlqx after vcc exceeds 3.3v. the p11c68 store cycle is initiated by executing sequential read cycles from six specific address locations.by relying on read cycles only, the p11c68 implements non- volatile operation while remaining pin-for-pin compatible with standard 8kx8 srams. during the store cycle, an erase of the previous non-volatile data is first performed, followed by a program of the non-volatile elements. the program operation copies the sram data into non-volatile storage. once a store cycle is initiated, further input and output are disabled until the cycle is completed. because a sequence of addresses is used for store initiation, it is critical that no invalid address states intervene in the sequence or the sequence will be aborted. the maximum skew between address inputs a0-12 for each address state is t skew (store cycle 1). if t skew is exceeded it is possible that the transitional data state will be interpreted as a valid address and the sequencewill be aborted. if e (bar) controlled read cycles are used for the sequence (store cycle 2), address skew is no longer a concern. to enable the store cycle the following read sequence must be performed. 1. read address 0000 (hex) valid read2. read address 1555 (hex) valid read 3. read address 0aaa (hex) valid read 4. read address 1fff (hex) valid read 5. read address 10f0 (hex) valid read 6. read address 0f0f (hex) initiate store cycle once the sixth address in the sequence has been entered, the store cycle will commence and the chip will be disabled.it is important that read cycles and not write cycles be used in the sequence, although it is not necessary that g (bar) be low for the sequence to be valid. after the t store cycle time has been fulfilled, the sram will again be activated forread and write operation. once the first of the six reads has taken place, the read sequence must either complete or terminate with an incorrectaddress (other than 0000 hex) before it may be started anew. the p11c68 offers hardware protection against inadvertent store cycles through vcc sense. a storecycle will not be initiated, and one in progress will discontinue, if vcc goes below 3.3v. a recall of the eeprom data into the sram is initiated with a sequence of read operations in a manner similar to thestore initiation. to initiate the recall cycle the following sequence of read operations must be performed: 1. read address 0000 (hex) valid read2. read address 1555 (hex) valid read 3. read address 0aaa (hex) valid read 4. read address 1fff (hex) valid read 5. read address 10f0 (hex) valid read 6. read address 0f0e (hex) initiate recall cycle internally, recall is a two step procedure. first, the sram data is cleared and second the non-volatile informationis transferred into the sram cells. the recall operation in no way alters the data in the eeprom cells. the non-volatile data can be recalled an unlimited number of times. address transitions may not occur during the recall cycle. p10c68/p11c68 15 on power-up, once vcc exceeds the vcc sense voltage of 3.3v, a recall cycle is automatically initiated. the voltageon the vcc pin must not drop below 3.3v once it has risen above it in order for the recall to operate properly. due to this automatic recall, sram operation cannot commence until t recall after vcc exceeds 3.3v. the automatic recall feature can be adversely affected by factors such as supply rise time, temperature and elapsedtime since the last store cycle. for this reason it is recommended that the user initiate a recall cycle after power-up for critical applications. package details dimensions are shown thus: mm (in). for further package information please contact your local customer servicecentre. 0.229/0.308 (0.009/0.012) 7.37/7.87 (0.290/0.310) 3.30/4.06 (0.130/0.160) 1.016/1.524(0.040/0.060) 7.620/8.128(0.300/0.320) pin 1 1.27 (0.050) typ 35.20/35.92 (1.386/1.414) 1.930/2.39 (0.05576/0.094) 0.36/0.51(0.014/0.020) 2.54(0.100) "# (7 $*$ 0' ! 8 pin 1 pin 1 ref. notch leads 0.3/0.55 (0.76/1.4) 1.37 (34.8) 0.02 (0.51) 0.015/0.02 (0.38/0.53) 0.1 (2.54) 0.2/0.3 0.12 (3.05) min 0.2 (5.08) max 0.288(7.32) nominal centres 0.3 (7.62) sea ting plane "# 3 %$ 0' $)# ! 8 p10c68/p11c6816 headquarters operationsgec plessey semiconductors cheney manor, swindon, wiltshire sn2 2qw, united kingdom. tel: (0793) 518000 tx: 449637 fax: (0793) 518411 gec plessey semiconductors sequoia research park, 1500 green hills road, scotts valley, california 95066, united states of america. tel (408) 438 2900 itt telex: 4940840 fax: (408) 438 5576 customer service centres france & benelux les ulis cedex tel: (1) 64 46 23 45 tx: 602858f fax : (1) 64 46 06 07 germany munich tel: (089) 3609 06-0 tx: 523980 fax : (089) 3609 06-55 italy milan tel: (02) 66040867 fax: (02) 66040993 japan tokyo tel: (03) 3296-0281 fax: (03) 3296-0228 north america integrated circuits and microwave products, scotts valley, usa tel (408) 438 2900 itt tx: 4940840 fax: (408) 438 7023.hybrid products, farmingdale, usa tel (516) 293 8686 fax: (516) 293 0061. south east asia singapore tel: 2919291 fax: 2916455 sweden johanneshov tel: 46 8 702 97 70 fax: 46 8 640 47 36 united kingdom & scandinavia swindon tel: (0793) 518510 tx: 444410 fax : (0793) 518582 these are supported by agents and distributors in major countries world-wide.? gec plessey semiconductors year publication no. xx xxxx issue no. x.x month year this publication is issued to provide information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. no warranty or guarantee express or implied is ma de regarding the capability, performance or suitability of any product or service. the company reserves the right to alter without prior knowledge the specification, design or price of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the us er's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. th ese products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subje ct to the company's conditions of sale, which are available on request. ordering information pxx c68 - xx / x g / dx bs package typec = ceramic p = plastic temperature range c = commercial i = industrial speed grade -35 = 35ns -45 = 45ns device numbereg. 10 = hardware store/recall 11 = software store/recall www .zarlink.com ! " # $ $ % ! & & ' $ % ( % & " ) * " ) * " ) * ) * " * )++, ( - - $.* *(/01*2'. $($1 # 1$31--.(/. for more inf ormation about all zarlink pr oducts visit our w eb site at |
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